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Posted: Monday, February 5, 2018 2:14 AM

Engineering Scientist - R and D Communications Designer
Hiring department
Applied Research Lab
Monthly salary
$6,250 - $10,833
Hours per week
40.00 Standard from 800AM to 500PM
Posting number
Job Status
FLSA status
Earliest Start Date
Position Duration
Funding expected to continue
Position open to
all applicants
Austin - J. J. Pickle Research Campus (North Austin)
Number of vacancies
General Notes
An agency designated by the federal government handles the investigation as to the requirement for eligibility for access to classified information. Factors considered during this investigation include but are not limited to allegiance to the U.S., foreign influence, foreign preference, criminal conduct, security violations, drug involvement, the likelihood of continuation of such conduct, etc.
Required Application Materials
+ A Resume is required in order to apply
+ A Letter of Interest is required in order to apply.
+ A List of 3 References is required in order to apply.
The following additional materials are also required for consideration:
Transcripts.References must be former employers.
Instructions for submission of these materials will be provided at the
time the online application has been completed.
Additional Information
Design, develop, and test signal processing and control software, firmware, and FPGA designs for radio frequency communications systems and sub-systems.
Essential Functions
Work as a member of a development team for the design, integration, and testing of signal processing software, firmware, and FPGA designs for digital wireless and wired communication systems and related sub-systems Develop and test software and/or firmware related to successful implementation and integration of signal processing software/firmware/FPGA elements Testing in both laboratory and field environments of hardware in either partial subsystems or full system and simulate relevant elements of the system. Documentation of all drawings, hardware, and software developed. Provide information about designs and tests to other team members both at ARL and at other organizations. Preparation of presentations of results, designs, or other related aspects of system design to both internal and external project directors as requested by supervisor
Marginal/Incidental functions
Other related functions as assigned.
Required qualifications
Bachelor's degree in electrical engineering and three years of experience with design and troubleshooting of electronic circuits at the component level. Experience in digital signal processing for communications with at least 1 year of work experience with FPGA programming (VHDL or Verilog) and debug. Experience with MATLAB or similar development software. The position will require attention to detail, effective problem solving, sound engineering judgment, and good communication skills. Interest in mixed-signal FPGA design (Digital interfaces to ADCs, DACs, etc.). Basic knowledge of embedded programming in C or C++. Basic knowledge of digital modulation, demodulation, equalization, FFTs, etc. Basic familiarity with DMM, oscilloscope, signal generators. US Citizen: Applicant selected will be subject to a government security investigation and must meet eligibility requirements for access to classified information at the level appropriate to the project requirements of the position.
Preferred Qualifications
MS in EE with core work in communications. Experience in a team-oriented engineering research and development environment. At least 3 years of work experience with FPGA programming (VHDL) and debug. Experience with MATLAB or similar prototyping and simulation software. Experience with mixed signal FPGA design (Digital interfaces to ADCs, DACs, etc.). Working knowledge of digital modulation, demodulation, equalization, FFTs, etc. Experience implementing communication systems functions in FPGA HDL. At least 1 year of experience with embedded software design in C or C++. Experience with Xilinx FPGAs and tools (ISE, Vivado, etc.). Three years or more experience with using DMM, oscilloscopes, logic analyzers, spectrum analyzers, signal generators, etc. Cumulative GPA of 3.0.
Working conditions
May work around standard office conditions
Repetitive use of a keyboard at a workstation
Use of manual dexterity
Lifting and moving
Some weekend, evening and holiday work. May work in shared, windowless office space. Possible intrastate/interstate travel.
A criminal history background check will be required
for finalist(s) under consideration for this position.
The retirement plan for this position is Teacher Retirement
System of Texas (TRS), subject to the
position being at least 20 hours per week and at least
135 days in length.
The University of Texas at Austin, as an equal opportunity/affirmative action employer, complies with all applicable federal and state laws regarding nondiscrimination and affirmative action. The University is committed to a policy of equal opportunity for all persons and does not discriminate on the basis of race, color, national origin, age, marital status, sex, sexual orientation, gender identity, gender expression, disability, religion, or veteran status in employment, educational programs and activities, and admissions.
If hired, you will be required to complete the federal Employment
Eligibility Verification form, I-9. You will be required to present
acceptable, original
to prove your identity and
authorization to work in the United States. Information
from the documents will be submitted to the federal E-Verify
system for verification. Documents must be
presented no later than the third day of employment. Failure to do
so will result in dismissal.
UT Austin is a Tobacco-free Campus
Associated topics: artificial intelligence, c c++, electrical, electronic, electronic engineering, javascript, matlab, python, robotics, software


• Location: Austin

• Post ID: 28889472 austin is an interactive computer service that enables access by multiple users and should not be treated as the publisher or speaker of any information provided by another information content provider. © 2018